The design of a wireless modem and its associated datapath is traditionally carried out with the help of a bit-exact simulation model that allows the designer to study the impact of finite precision arithmetic at various points in the datapath. It is usually possible to break a modem transmitter or receiver into a cascade of processing blocks and then approach the design of each block separately (although inter-block dependencies must be taken into account, as discussed below). The simple OFDM receiver in the figure below is a typical example. When designing a processing block, It is common practice to first develop a floating point version, verify this version by simulation and then develop a second version in integer arithmetic, which is also verified by simulation. The objective is to ensure that the integer version, with bitwidths set appropriately, produces an output that deviates only slightly from that of the floating point version. When this approach is used, it often becomes necessary to simulate the system with some blocks operating in floating point mode and some operating in integer mode, or even switch the operation of individual blocks back and forth between floating point mode and integer mode. MATLAB's object-oriented features are a great help when creating this type of simulation model, with processing blocks modeled as objects that are configurable with respect to bitwidths, arithmetic mode etc. Object aggregation can be used to create hierarchical models, where one block is implemented as a network of simpler blocks.
Once a bit-true simulation model of the modem has been developed, an attempt is usually made to optimize the bitwidths in the datapath. This is essentially a trial-and-error process, where adjustments are made to some of the bitwidths and the impact is then evaluated by simulation, using error rate or EVM (Error Vector Magnitude) as a performance metric. Based on the simulation results, new bitwidth adjustments are made, followed by another simulation run, and so on. Overall, the "traditional" method outlined above tends to be quite time-consuming, due to the long simulation runs that are needed when datapath parameters are set by trial-and-error. Even worse, because of dependencies that exist between the processing blocks, it is often necessary to define and simulate the entire modem in integer arithmetic before any individual block can be released to the digital design team for RTL coding. This means that the system design task and digital design task cannot proceed concurrently and must be carried out in sequence, creating a bottleneck in the design cycle. To break the bottleneck, the system designer must be able to finalize the design of some blocks while the rest of the modem remains partially unspecified. However, this is difficult to achieve with a design methodology based on simulation. To illustrate this, let us consider the Gain Control block in the figure above. Suppose that we wish to issue a firm specification of this block before any of the other parts of the modem have been completely defined. The specification of the Gain Control block includes its output bitwidth However, suppose instead that we use an approach where individual blocks are given a "black box" specification based on gain and noise figure (see here for information on how to define the noise figure for a digital processing block). Note that a DSP block can always be designed in such a way that both the gain and the noise figure are functions of the difference between the input and output bitwidths. For instance, the FFT block above can be designed so that its gain and noise figure are functions of w
All quantities on the right hand side are functions of the inter-block bitwidths (
w_{1},w_{2},w_{3},w_{4}). Consequently, for each choice of vector (w_{1},w_{2},w_{3},w_{4}), there is a corresponding noise factor value. Note that the input bitwidth w_{0} is typically given in the design specification for the modem and should not be considered a design variable here. The dependencies between the blocks in the modem can now be resolved by selecting a vector (w_{1},w_{2},w_{3},w_{4}) that meets the noise figure requirement. Suppose that we have defined a set of feasible bitwidth vectors (usually limited to a few thousand vectors). A computer algorithm can then be used to evaluate the noise figure of each vector and discard those vectors that do not meet the noise figure requirement. Among the surviving vectors, the minimum value of w_{1 }is identified, and the vectors with non-minimum w_{1 }are eliminated. If only one vector remains at this point, we are done. If not, the elimination continues by focusing on the bitwidth that is considered the second most critical for the hardware cost of the modem. In the example above, this would be w_{2}. Hence, the minimum value of w_{2} in the set of survivors is now identified and those vectors with non-minimum w_{2} are eliminated. The procedure is repeated until only one vector remains.Other inter-block dependencies may exist. For instance, the phase estimate bitwidth Back to Custom DSP Solutions
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